Single -chip machine/SWD: Download the principles of the bottom layer of communication

Based on the Cortex-M kernel, the mainstream download interface is JTAG and SWD.

SWD and JTAG pin differences:

JTAG：

• TDI：Test data in.Serial input pins

• TDO：Test data out, serial output pins

• TCK：Test Clock, clock pin

• TMS：Test Mode Select, mode selection (control signal) pins

• TRST：Test Reset, reset pin

SWD：

• SWDIO：Serial wire data input output, serial data input output pins

• SWCLK：Serial Wire Clock, serial line clock

Among them, SWD only requires two lines (SWCLK and SWDIO). In the case of limited PCB layout and tight pins resources, SWD is a good choice.

SWD: Serial Wire Debug, representing the traversing line debuggingIt is an ARM design protocol for programming and debugging its microcontroller.

There are many downloaders that support SWD debugging interfaces on the market, such as:ST-Link、 J-Link、 e-Link、 GD-LinkMost of the downloaders used on the market for Cortex-M kernel processors are supported.

For SWDIO, it is a two -way (input and output) data pin. The line must be pulled on the circuit board (100 K is recommended to use ARM).

Every time the direction of SWDIO is changed in the protocol, the conversion time is inserted. At this time, the line is not driven by the host or the target driver.By default, this conversion time is one time, but it can be adjusted by configuring the SWCLK frequency.

Common Cortex-M kernel processors are integratedSWD and JTAG debug portIn SWJ-DP, the 2 JTAG pins of SW-DP and the 5 JTAG pins of JTAG-DP's 5 JTAG pinsPartial pins。

The switch mechanism of JTAG and SWD:

The default debugging interface is the JTAG interface. If the debugging tool wants to switch to SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK (respectively map to SWDIO and SWCLK) to prohibit JTAG-DP and enable SW-SW-DP.In this way, you can use SWCLK and SWDIO pins to activate SWDP.

This sequence is:

1. Output more than 50 TCK cycles TMS (SWDIO) = 1 signal

2. Output 16 TMS (SWDIO) signals 01111100111100111 (MSB)

3. Output more than 50 TCK cycles TMS (SWDIO) = 1 signal

Each sequence includes three stages:

• Data packet request sent by the host (8 bits)

• Confirmation response of target sending (3 digits)

• Data transmission phase sent by the host or target (33 digits)

Package request (8 digits):

ACK response (3 digits):

Data transmission (33 digits)

Some of the bits similar to the register, some principles andOrdinary communication protocolThere are similarities.Essence

SW-DP status machine has an internal ID code for identifying SW-DP, which mainly contains the status: reset, idle state, ID code, etc.

• After the power-on reset, after the DP is switched from JTAG to SWD or the line is at a high level of more than 50 cycles, the SW-DP state machine is in a reset state.

• If the line is at least two cycles at a low level after the reset state, the SW-DP state machine is idle.

• After the reset state, the state machine must first enter the idle state, and then perform a visit to the DP-SW ID code register.Otherwise, the target will issue a FAULT confirmation response in another transaction.

For more details of the SW-DP status machine, you can seeCortex-m related manuals。

SWD is similar to ordinary peripherals, and it is also a register. The programming (read and write) operation performed by the developer is actually the corresponding register.

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